1. Field of the Invention
The present invention relates to a recovery circuit generating a reproduction clock in synchronism with received data in a receiving section of a communication apparatus and particularly, to a recovery circuit generating a low jitter reproduction clock.
2. Description of the Background Art
A recovery circuit generating a reproduction clock based on received data in a receiving section of a communication apparatus transmitting/receiving data compares a phase of reproduction clock with a phase of received data to have the reproduction clock to be synchronized with the received data. Received data in the receiving section is a NRZ (Non-Return Zero) signal and a reproduction clock is a RZ (Return Zero) signal; therefore comparison of both in phase has to be performed at edges of the data.
Referring to FIG. 24, a conventional phase comparator circuit 500 included in a recovery circuit is constituted of: flip-flops 510 and 520; and EX-OR gates 530 and 540. The flip-flop 510 is driven in synchronism with the rising edge of a reproduction clock CLK, receives received data DIN as an input signal to output output signals to the flip-flop 520 and the EX-OR gates 530 and 540. The flip-flop 520 is driven in synchronism with the falling edge of the reproduction clock CLK, receives an output signal of the flip-flop 510 and outputs an output signal to the EX-OR gate 540. The EX-OR gate 530 receives the received data and an output signal of the flip-flop 510 as input signals, performs an exclusive OR operation on the two input signals to output an up signal UP. Further, the EX-OR gate 540 receives an output signal of the flip-flop 510 and an output signal of the flip-flop 520 as inputs, performs an exclusive OR operation on the two signals to output a down signal DWN.
Referring to FIG. 25B, when a reproduction clock CLK is delayed as compared to received data in phase, the flip-flop 510 outputs a signal D1 in synchronism with the rising edge of the reproduction clock CLK, while the exclusive OR gate 530 performs an exclusive OR operation on the received data DIN and the signal D1 to output an up signal UP. Further, the flip-flop 520 holds the output signal D1 of the flip-flop 510 in synchronism with the falling edge of reproduction clock CLK to output a signal D2. The exclusive OR gate 540 performs an exclusive OR operation on the signals D1 and D2 to output a down signal DWN. In this case, a width of the up signal UP is larger than that of the down data DWN. Accordingly, when the reproduction clock CLK is delayed as compared to the received data DIN in phase, the phase comparator circuit 500 outputs the up signal UP with a larger width.
Further, with reference to FIG. 25C, when reproduction clock CLK leads received data DIN in phase, a width of a down signal is larger than that of an up signal UP. Accordingly, when the reproduction clock CLK leads the received data DIN in phase, the phase comparator circuit 500 outputs a down signal DWN with a larger width.
Referring to FIG. 25A, when a phase of a reproduction clock CLK coincides with a phase of received data DIN, the phase comparator circuit 500 outputs an up signal UP and a down signal DWN, both of the same width.
That is, the phase comparator circuit 500 outputs an up signal UP and a down signal DWN, when an edge of received data is inputted, in any of cases where in phase, a reproduction clock CLK is delayed as compared to received data DIN, leads data DIN and coincides with data DIN. When reproduction clock CLK is delayed as compared to received data DIN in phase, a phase of the reproduction clock CLK is adjusted such that a width of an up signal is narrowed and comes to be the same as that of a down signal. Further, when reproduction clock CLK leads received data in phase, a phase of the reproduction clock CLK is adjusted such that a width of a down signal DWN is narrowed and comes to be the same as that of an up signal UP.
Phase adjustment of a reproduction clock is performed by an operation in which a control voltage based on a comparison result in phase of the phase comparator circuit 500 is outputted to a voltage controlled oscillator and a phase of the reproduction clock CLK is altered according to a level of the control voltage. That is, a capacitor is connected between an output node supplying a control voltage to the voltage controlled oscillator and a ground node, an electric charge corresponding to a width of an up signal is charged in the capacitor to raise the control voltage or an electric charge corresponding to a width of a down signal is discharged from the capacitor to lower the control voltage, whereby the control voltage is adjusted such that a phase of a reproduction clock CLK coincides with a phase of received data DIN.
Hence, when reproduction clock CLK is delayed as compared to received data DIN in phase, charging of the capacitor by an up signal UP and discharging of the capacitor by a down signal DWN are alternately repeated and in such repetitions of charging and discharging, a charge time of the capacitor by up signals is adjusted to be totally longer than a discharge time of the capacitor by down signals, with the result that the control voltage gradually rises. Further, when a reproduction clock CLK leads received data DIN in phase, charging of the capacitor by an up signal UP and discharging of the capacitor by a down signal DWN are alternately repeated and in such repetitions of charging and discharging, a discharge time of the capacitor by down signals DWN is adjusted to be totally longer than a charge time of the capacitor by up signals UP, with the result that the control voltage gradually falls. Still further, when a phase of reproduction clock CLK coincides with a phase of received data DIN, charging of the capacitor by up signals UP and discharging of the capacitor by down signals DWN are alternately repeated such that a charge time of the capacitor by up signals UP and a discharge time by down signals DWN are totally equal to each other and as a result, the control voltage is held unchanged, as a whole, though process.
In a prior art recovery circuit, however, even when a phase of a reproduction clock CLK coincides with a phase of received data DIN, an up signal and a down signal are repeatedly outputted at edges of received data; therefore charging of the capacitor by up signals UP and discharging of the capacitor by down signals DWN are repeated such that a control voltage supplied to a voltage controlled oscillator is held at a constant value. With such an operation adopted, when intervals between the charging and the discharging are gradually longer, a problem arose since the timing of voltage adjustment in the voltage controlled oscillator is shifted, thereby producing jitter in the reproduction clock CLK.
The present invention has been made in order to solve such a problem and it is accordingly an object of the present invention is to provide a recovery circuit capable of generating a low jitter recovery clock regardless of an operating frequency.
A recovery circuit according to the present invention includes: a phase comparator circuit comparing a phase of a reproduction clock with a phase of received data, outputting an up signal when the reproduction clock is delayed as compared to the received data in phase and an edge of the received data has been detected in a first period in which the reproduction clock is a first logic, and outputting a down signal composed of a first component having detected an edge of the received data in a second period in which the reproduction clock is a second logic and a second component having detected that a logic of the received data is constant in the second period when the reproduction clock leads the received data in phase; a control voltage adjusting circuit raising a control voltage when the up signal is inputted, lowering the control voltage when the first component of the down signal is inputted and canceling the second component of the down signal to hold the control voltage when the second component of the down signal is inputted; and a voltage controlled oscillator generating a reproduction clock whose phase is altered according to a level of the control voltage to output the generated reproduction clock to the phase comparator circuit.
In a recovery circuit according to the present invention, when a reproduction clock is delayed as compared to received data in phase, an up signal having detected an edge of the received data is outputted to the control voltage adjusting circuit from the phase comparator circuit. Further, when the reproduction clock leads the received data in phase, a first component of a down signal having detected an edge of the received data is outputted to the control voltage adjusting circuit from the phase comparator circuit. Furthermore, a second component of the down signal bearing no relation to an edge of the received data is also detected and outputted to the control voltage adjusting circuit from the phase comparator circuit. In this situation, the control voltage adjusting circuit not only raises or lowers a voltage level of a control voltage based on the up signal or the first component of the down signal to adjust the control voltage, but also cancels the second component of the down signal. Then, the voltage controlled oscillator adjusts a phase of the reproduction clock based on the control voltage from the control voltage adjusting circuit. Hence, according to the present invention, not only can a phase of a reproduction clock be forced to coincide with a phase of received data, but a low jitter reproduction clock can also be generated in this coincidence state.
The control voltage adjusting circuit preferably includes: a loop filter raising or lowering the control voltage based on a supplied electric charge; a charge pump circuit supplying a first electric charge for raising the control voltage based on the up signal and supplying a second electric charge for lowering the control voltage based on the down signal; and a sampling circuit supplying the first electric charge to the loop filter circuit, and supplying the second electric charge to the loop filter circuit after holding the second electric charge for a prescribed period when the first component is inputted and canceling the second electric charge when the second component is inputted.
In the control voltage adjusting circuit, when an up signal is inputted, a first electric charge is supplied to the loop filter from the charge pump circuit to raise a control voltage. Further, when the first component of a down signal is inputted, the charge pump circuit supplies a second electric charge to the loop circuit through the sampling circuit. That is, the charge pump circuit receives an electric charge corresponding the first component from the sampling circuit and the sampling circuit receives an electric charge corresponding to the first component from the loop filter circuit, and thereby the second electric charge for lowering the control voltage is transmitted to the loop filter circuit from the charge pump circuit. Furthermore, when the second component is inputted, the charge pump circuit supplies the second electric charge to the sampling circuit and the sampling circuit cancels the second electric charge. The loop filter circuit then raises the control voltage based on the first electric charge supplied and lowers the control voltage based on the second electric charge supplied. Hence, according to the present invention, an up signal and a first component of a down signal are transmitted to the loop filter circuit with supply of an electric charge and a second component of the down signal is transmitted to the sampling circuit with supply of an electric charge and thereby canceled; therefore, phase adjustment of a reproduction clock and generation of a low jitter clock can be realized by an analog circuit.
It is preferable that the phase comparator circuit of the recovery circuit further outputs a transmission signal for transmitting the second electric charge to the loop filter circuit when the first component is inputted and a reset signal for canceling the second electric charge when the second component is inputted; and the sampling circuit performs sampling of and holds the second electric charge when the down signal is inputted to the charge pump circuit, is rendered to be conductive with the loop filter when the transmission signal is inputted, and holds the control voltage at a constant level and equalizes a sampling value to the control voltage when a reset signal is inputted.
The sampling circuit discharges an electric charge to the charge pump circuit to reach the second electric charge and receives an electric charge equal to the discharged electric charge as supplement from the loop filter circuit to transmit the first component to the loop filter circuit. Further, the sampling circuit discharges an electric charge to the charge pump circuit to reach the second electric charge and receives an electric charge equal to the discharged electric charge as supplement from the loop filter circuit while holding the control voltage at a constant level, thereby canceling the second component of a down signal. Hence, according to the present invention, a function to transmit the first component of a down signal can be separated from a function to cancel the second component of the down signal, thereby enabling setting of longer processing times for the respective components. As a result, a low level of jitter even in a reproduction clock of a high frequency can be realized.
The recovery circuit preferably includes a plurality of sampling circuits connected in parallel between the charge pump circuit and the loop filter circuit.
An operation to transmit the first component of a down signal to the loop filter circuit and an operation to cancel the second component of the down signal are shared by a plurality of sampling circuits. Hence, according to the present invention, one operation can be performed by a plurality of the sampling circuits; therefore a longer processing time can be set for the one operation. As a result, a low jitter reproduction clock can be generated even in a case of a frequency multiplied by the number of sampling circuits.
The sampling circuit preferably includes: a capacitance element performing sampling of and holding the second electric charge discharged from the charge pump; a first switch controlled by a transmission signal; a second switch controlled by a reset signal; and an analog buffer equalizing the capacitance element to the control voltage.
The capacitance element performs sampling of and holds the second electric charge released from the charge pump circuit. When a transmission signal is inputted, then the first switch is turned on to transmit the second electric charge to the loop circuit, while when a reset signal is inputted, then the second switch is turned on and an electric charge is supplied from the analog buffer to cancel the second electric charge. Hence, according to the present invention, a sampling circuit can be easily realized using a capacitance element.
The control voltage adjusting circuit of the recovery circuit preferably cancels the second component of a down signal in a digital signal processing. The control voltage adjusting circuit cancels the second component inputted from the phase comparator circuit in a digital processing. Hence according to the present invention, the second component can be canceled at high speed.
It is preferable that the voltage controlled oscillator of the recovery circuit further generates a plurality of clocks with different phases, and the control voltage adjusting circuit includes: an output node supplying the control voltage to the voltage controlled oscillator; a sampling circuit receiving the plurality of clocks as inputs, performing sampling of the first and second components of the down signal inputted from the phase comparator circuit according to the plurality of clocks to recover the first component only and output a recovered signal thereof; a charge pump circuit supplying the first electric charge for raising the control voltage to the loop filter circuit based on the up signal from the phase comparator circuit and receiving/supplying the second electric charge for lowering the control voltage from the loop filter circuit based on the reproduction signal from the sampling circuit; and a loop filter circuit raising the control voltage on the output node based on the first electric charge and lowering the control voltage on the output node based on the second electric charge.
The sampling circuit cancels the second component of the down signal inputted from the phase comparator circuit and reproduces only the first component to generate a reproduced signal based on the first and second components of the down signal and a plurality of clocks. The charge pump circuit supplies the first electric charge to the loop filter circuit based on an up signal from the phase comparator circuit and further supplies the second electric charge to the loop filter circuit based on the reproduced signal from the sampling circuit. The loop filter circuit raises or lowers the control voltage based on the first and second electric charges. That is, in a signal processing stage, after the second component is canceled and only the first component is reproduced, supplying/receiving of an electric charge are performed to adjust the control voltage. Hence, according to the present invention, the second component can be canceled without supplying/receiving of an electric charge.
It is preferable that the phase comparator circuit of the recovery circuit further outputs a reset signal and the sampling circuit cancels the second component of the down signal when the reset signal is sampled in succession to sampling of the second component of the down signal according to the plurality of clocks.
When a reset signal is sampled according to the plurality of clocks in succession to sampling of the second component according to the plurality of clocks, the second component is canceled. Therefore, the second component can be canceled according to the presence or absence of a reset signal.
It is preferable that the sampling circuit generates the reproduced signal such that a current is held constant and a time length for which the current is forced to flow is altered according to a width of the first component of the down signal and thereby, the charge pump circuit receives/supplies the second electric charge.
The sampling circuit assigns a weight, associated with a width of the first component of a down signal, to a time length for which a current flows into the charge pump circuit in generating a reproduced signal. Thereby, a current flows into the charge current circuit for a time length determined based on the reproduced signal and thus the charge pump circuit receives/supplies the second electric charge. Hence, according to the present invention, a time length for which a current flows into the loop filter circuit is altered according to a width of the first component of a down signal, thereby enabling supplying/receiving of an electric charge necessary for the first component to be transmitted to the loop filter circuit.
It is preferable that the sampling circuit generates the reproduced signal such that a time length for which a current flows is held at a constant value and a current value is altered according to a width of the first component of the down signal, and thereby the charge pump circuit receives/supplies the second electric charge.
The sampling circuit assigns a weight, associated with a width of the first component of a down signal, to a current value at which a current flows into the charge pump circuit in generating a reproduced signal. A current with a value determined based on the reproduced signal flows into the charge current circuit such that the charge pump circuit receives/supplies the second electric charge. Hence, according to the present invention, a current value at which a current flows into the loop filter circuit is altered according to a width of the first component of a down signal and thereby, enabling supplying/receiving of a electric charge necessary for the first component to be transmitted to the loop filter circuit.